The present invention relates to a method for fabricating a bipolar transistor, particularly to an improvement in the reliability of contact to the emitter of a bipolar transistor having a self-aligned base and emitter.
To increase the packing density and the operation speed of bipolar ICs or LSIs, a scale down in size and an improvement in the performance of bipolar transistors incorporated therein are indispensable. For this end, a dielectric isolation technology using insulating layers is substituted for the p-n junction isolation in order to decrease the size of the bipolar transistors. Also, a shallow base and emitter structure is employed for providing a thin base region necessary for the high speed operation, thereby improving the high frequency characteristics. There are disclosed various fabrication methods for providing bipolar transistors as mentioned above, including the most popular one referred to as "isoplanar technology".
For instance, "Self-Aligned Bipolar Transistors for High-Performance and Low-Power-Delay VLSI", IEEE, Transaction on Electron Device, Vol.ED-28, No.9, September 1981, pp. 1010-1013 describes a bipolar transistor having a self-aligned base and emitter regions formed shallow and adjacent to the surface of a semiconductor substrate by ion injections. FIG. 1 is a cross-section illustrating an exemplary configuration of a bipolar transistor fabricated in accordance with the disclosure. Referring to FIG. 1, shallow base region 51 and emitter region 61 are formed adjacent to the surface of a semiconductor substrate 40 having p-type conductivity, for example. The shallow and thin intrinsic base region 51 is connected to a base terminal 52 via an extrinsic base region 53 which is formed by diffusing p-type impurities from a doped polysilicon layer 54. The emitter region 61 is connected to an emitter terminal 62 which is insulated from the polysilicon layer 54 by oxide layers 55 and 56. The oxide layer 55 is formed on the side wall surface of an opening which is provided in the polysilicon layer 54. The oxide layer 56 is formed on the polysilicon layer 54. The collector region of the transistor is connected, as conventional, to a collector terminal 63 via a buried layer 64 and an N collector contact region 65. Because the base region 51 and emitter region 61 are self-aligned thanks to the opening formed in the polysilicon layer 54, and also, the base terminal 52 is formed on the isolation oxide layer 41, the bipolar transistor can have high performance and become suitable to use with high density integrated circuits.
However, in the structure as shown in FIG. 1, the contact to the emitter region 61 is formed in a recess which is deep from the top surface of the surrounding layer 56. Accordingly, the connection to the emitter region 61 must be established through a steep step as large as about 1 micron in the emitter terminal 62. The steep and large step should produce a faulty coverage in the conductor layer formed thereon. Such faulty step coverage sometimes becomes apparent, when resulting in a disconnection in the emitter contact, after a long operation of the bipolar transistor in the field. Thus, the faulty step coverage decreases the reliability of equipment or a system comprising such kind of bipolar transistors.